Conventional PVDs generally fall into two categories—a first type that uses Si substrates and Si-based materials for active photovoltaic (PV) regions and a second type that uses Ge or GaAs substrates with one or more active PV regions constructed using lattice-matched III-V compound semiconductor materials. Conventional Si-based PVDs generally have lower conversion efficiency than PVDs based on Ge or GaAs substrates (e.g., 10-15% vs. 20-40%). Si-based PVDs are less expensive to make than Ge or GaAs-based PVDs. PVDs built on Si substrates generally cost less than PVDs built on Ge or GaAs substrates. But PVDs built on Ge or GaAs substrates generally have higher performance (efficiency) than PVDs built on Si substrates.
The development of high-efficiency III-V compound solar cells grown on Si substrates is of particular interest for space and terrestrial PVDs. In comparison with GaAs and Ge, the currently the dominant substrates for III-V space photovoltaics, Si possesses far superior substrate properties with respect to mass density, mechanical strength, thermal conductivity, cost, wafer size and availability. However, the fundamental material incompatibility issues between III-V compounds and Si still represent a substantial hurdle for achieving high-performance Si-based III-V PV cells. These material incompatibility issues include lattice mismatch between III-V compounds and Si and a large mismatch in thermal expansion coefficiency. The high density of dislocations that occur at interfaces between Si and III-V compounds leads to low minority-carrier lifetime and results in low open-circuit voltages. To date, progress has been made in reducing GaAs dislocation density by employing various epitaxial schemes such as cycle thermal annealing, epitaxial lateral overgrowth, growth on compositional graded SiGe buffers, and insertion of strained layer superlattices. See, respectively, M. Yamaguchi, A. Yamamoto, M. Tachikawa, Y. Itoh and M. Sugo, Appl. Phys. Lett. 53 2293 (1998); Z. I. Kazi, P. Thilakan, T. Egawa, M. Umeno and T. Jimbo, Jpn. J. Appl. Phys. 40, 4903 (2001); M. E. Groenert, C. W. Leitz, A. J. Pitera and V. Yang, Appl. Phys. Lett. 93 362 (2003); and N. Hayafuji, M. Miyashita, T. Nishimura, K. Kadoiwa, H. Kumabe and T. Murotani, Jpn. J. Appl. Phys., 29, 2371 (1990), all incorporated by reference herein. Unfortunately, these methods generally require relatively thick transition layers—typically greater than 10 micrometers (μm)—before device quality materials are obtained, which is not viable for practical applications.
Aspect ratio trapping (ART) technology enables the growing of high quality lattice-mismatched materials such as Ge or GaAs (or other III-V materials) on Si substrates, as described in U.S. patent application Ser. Nos. 11/436,198, 11/728,032, and 11/852,078, all incorporated by reference herein. Using Si substrates and ART technology to provide relatively high quality Ge or GaAs layers allows for building PVDs that have the advantages of Si substrates (e.g., cost, manufacturing, thermal performance, radiation resistance, strength) as well as advantages of PVDs built using Ge or GaAs substrates (e.g., high efficiency).
An advantage of using ART for PV is that isolating ART regions from each other prevents the performance of a cell from being affected by a problematic neighboring cell, e.g., by recombination of electrons and holes due to defects. Another advantage of ART for PVs is that it allows the combination of two materials that have mismatched thermal expansion properties, such as Si and III-V materials. As with the trapping of defects in the ART region, expansion mismatch and associated challenges are confined to small areas.
In an aspect, embodiments of the invention feature a structure for use in photovoltaic applications. The structure includes a mask layer that is disposed above the top surface of a substrate. The mask layer includes a non-crystalline material, and has an opening extending from the top surface of the mask layer to the top surface of the substrate. A crystalline material may be disposed in the opening and may have a first region disposed above and proximal to a portion of the top surface of the substrate. A second region of the crystalline material, which may have substantially fewer defects than the first region, may be disposed above the first region and the top surface of the substrate. A photovoltaic cell may be disposed above the crystalline material.
One or more of the following features may be included. The substrate may include at least one of monocrystalline silicon, e.g., (111) silicon, polycrystalline silicon, or amorphous silicon. The substrate may include a material having a lattice mismatch with the crystalline material. The mask layer may include an oxide of silicon and/or a nitride of silicon, and may include first and second layers made of different chemical compositions. The crystalline material may include a III-V compound, e.g., a III-nitride material, a II-VI compound, or a group IV element or compound.
The photovoltaic cell may include one or more of a multi junction photovoltaic cell, an active cell junction above and/or below the top surface of the mask layer, or an active cell junction below the top surface of the substrate. The active cell junction below the top surface of the substrate may have a shape corresponding to a shape defined by an intersection of the opening in the mask layer and the top surface of the substrate. The active cell junction below the top surface of the substrate may include a doped layer proximal to the top surface of the substrate. The active cell junction below the top surface of the substrate may include a doped layer proximal a bottom surface of the substrate. An electrical contact may be disposed on a bottom surface of the substrate.
The opening may define a generally circular shape and/or a generally rectangular shape on the top surface of the substrate. The shape may have a length less than about 1 micrometer or greater than about 1 millimeter, and a width less than or equal to about 1 micrometer. The distance from the top surface of the mask layer at the opening to the top surface of the substrate may be less than or greater than about 1 micrometer in height, and the height may be greater than the width. The length may be greater than twice the width, and the width may be between about 100 nanometers to about 1 micrometer, between about 10 nanometers and about 50 nanometers, or between about 50 nanometers and about 100 nanometers.
In another aspect, an embodiment of the invention includes a structure for use in photovoltaic applications. The structure includes a substrate and a mask layer disposed above a top surface of the substrate. The mask layer may include a non-crystalline material and may have a plurality of openings extending from a top surface of the mask layer to the top surface of the substrate. A crystalline material, which may be disposed in and above the plurality of openings, may have a portion disposed above the openings having substantially fewer defects than a second portion of the crystalline material disposed within the openings and adjacent to the top surface of the substrate. A photovoltaic cell may be disposed above the crystalline material.
In various embodiments, the crystalline material includes at least one of a III-V compound, a II-VI compound, or a group IV element or compound. The III-V compound may include a III-nitride material. The mask layer may include an oxide of silicon and/or a nitride of silicon. The photovoltaic cell may include an active cell junction below the top surface of the substrate and/or a multi junction photovoltaic cell. The crystalline material may be disposed adjacent a top surface of the substrate, and an intermediate crystalline material may be disposed in the plurality of openings between the crystalline material and the substrate. At least one opening may define a generally circular shape on the top surface of the substrate, and the shape may have a length and a width, and the width may be less than about 1 micrometer. The length may be less than about 1 micrometer or greater than about 1 millimeter.
Each of the plurality of openings may have a height defined by the distance from the top surface of the mask layer to the top surface of the substrate, and each height may be less than or greater than about 1 micrometer. Each of the plurality of openings may define a shape on the top surface of the substrate, each shape may have a length and a width, and each width may be between about 100 nanometers and about 1 micrometer, between about 50 nanometers and about 100 nanometers, or between about 10 nanometers and about 50 nanometers. The length of each of the plurality of openings may be greater than twice the width of each of the plurality of openings. Each of the plurality of openings has a height defined by a distance from the top surface of the mask layer to the top surface of the substrate, and the height of each opening may be greater than or less than the width of each opening.
In yet another aspect, an embodiment of the invention includes a structure for use in photovoltaic applications. The structure includes a mask layer including a non-crystalline material, disposed above a top surface of a substrate. An opening may extend from a top surface of the mask layer to the top surface of the substrate, and may define a shape on the top surface of the substrate having a width less than about 1 micrometer and a length. A crystalline material may be disposed in the opening, and a photovoltaic cell, which may have at least one active cell junction having a width less than about 1 micrometer, may be disposed above the crystalline material.
One or more of the following features may be included. The length may be less than about 1 micrometer or greater than about 1 millimeter. The opening may have a height, which may be less than or greater than about 1 micrometer, defined by a distance from the top surface of the mask layer to the top surface of the substrate. The width may be between about 100 nanometers and about 1 micrometer, between about 50 nanometers and about 100 nanometers, or between about 10 nanometers to about 50 nanometers. The height may be greater than the width.
The photovoltaic cell may include a multi junction photovoltaic cell, one or more active cell junctions disposed above and/or below the top surface of the mask layer, or an active cell junction disposed below the top surface of the substrate. The crystalline material may include at least one of a III-V compound, a II-VI compound, or a group IV element or compound, and the III-V compound may include a III-nitride material. The mask layer may include an oxide of silicon and/or a nitride of silicon. An intermediate crystalline material may be disposed in the plurality of openings between the crystalline material and the substrate. The intermediate crystalline material may include at least one of a III-V compound, a II-VI compound, or a group IV element or compound. The intermediate crystalline material may be disposed adjacent to or in the opening adjacent to the top surface of the substrate and may have a thickness sufficient to permit a majority of defects arising in the intermediate crystalline material near the top surface of the substrate to exit the intermediate crystalline material at a height below the top surface of the mask layer.
In still another aspect, an embodiment of the invention includes a structure for use in photonic applications. A mask layer is disposed above a top surface of a substrate and includes an opening extending from a top surface of the mask layer to the top surface of the substrate. A crystalline material may be disposed in the opening, and a photonic device, which may have an active junction including a surface that extends in a direction substantially away from the top surface of the substrate, may be disposed above the crystalline material.
One or more of the following features may be included. The surface of the active junction is substantially perpendicular to the top surface of the substrate. The opening may define a generally columnar shape or a shape on the top surface of the substrate having a length and a width, and the width may be approximately equal to the length, less than half the length, or less than one tenth the length. The photonic device may include one or more active junctions having a sidewall surface that extends substantially away from the top surface of the substrate and that may be coupled to a top surface. The active junction surfaces may be substantially perpendicular to the top surface of the substrate. Each active junction may include a sidewall surface extending in a direction substantially away from the top surface of the substrate and coupled to a top surface. Each active junction may include a portion adjacent the top surface of the mask layer, and the mask layer may electrically isolate each active junction from the substrate. A portion of the active junction may be adjacent the top surface of the mask layer and the mask layer may electrically isolate the active junction from the substrate.
The crystalline material may include a III-V compound, a II-VI compound, and/or a group IV element or compound. The III-V compound may include a III-nitride material. The top surface of the mask layer may be substantially optically reflective. An active cell junction may be disposed below the top surface of the substrate, and may include a doped layer proximal to the top and/or bottom surface of the substrate. The photonic device may include a photovoltaic device, a plurality of multi junction photovoltaic devices, an LED, and/or a plurality of LEDs connected in parallel.
In another aspect, embodiments of the invention include a structure. A first semiconductor material, disposed on a substrate, includes a sidewall extending away from the substrate. A second semiconductor layer may be disposed on a portion of the sidewall to define an active device junction region. A mask layer, which may be disposed on the substrate adjacent to a bottom region of the sidewall, may electrically isolate the second semiconductor layer from the substrate.
One or more of the following features may be included. A third semiconductor layer may be disposed on the second semiconductor layer, and the mask layer may electrically isolate the third semiconductor layer from the substrate. The mask layer may define an opening, through which the first semiconductor material may be disposed on the substrate, having a sidewall extending a predefined height from a top surface of the mask layer to a top surface of the substrate. The opening may define a width and a length adjacent the top surface of the substrate, and the ratio of the height to the width may be greater or less than 1. The first semiconductor material may include at least one of a III-V compound, a II-VI compound, or a group IV element or compound, and the III-V compound may include a III-nitride material. The structure may include a photonic device, and the photonic device may include the active device junction region. The photonic device may include a photovoltaic device, a plurality of multi-junction photovoltaic devices, an LED, and/or a plurality of LEDs connected in parallel.
In still another aspect, embodiments of the invention include a structure. A first photonic device structure is disposed above a first region of a substrate and including a first top surface and a first uncovered sidewall surface. A second photonic device structure may be disposed above a second region of the substrate, may be spaced apart from the first structure, and may include a second top surface and a second uncovered sidewall surface. A conductive layer may extend from the first top surface of the first photonic device structure to the second top surface of the second photonic device structure, above the first and second uncovered sidewall surfaces of the first and second structures, to electrically couple the first and second top surfaces. The conductive layer may include aluminum (Al), silver (Ag), titanium (Ti), tin (Sn), chromium (Cr), and/or Si.
In another aspect, embodiments of the invention include a structure for use in photonic applications. A mask layer is disposed on a top surface of a substrate. The mask layer has a top surface, and a maximum height between the top surface of the substrate and the top surface of the mask of less than about 1 micrometer. A plurality of openings extend from the top surface of the mask to the top surface of the substrate, and may have a maximum width in one direction of less than about one micrometer. A crystalline material is disposed in each of the openings on the top surface of the substrate, and has a height sufficient to permit a majority of defects arising from the interface between the crystalline material and the substrate to exit the crystalline material below the top surface of the mask.
In yet another aspect, embodiments of the invention include a structure for use in photovoltaic applications. A photovoltaic device may be disposed on the top surface of the substrate, and may have a length and a width in a plane defined by the top surface of the substrate. The width may be approximately equal to a wavelength of light selected from a range of 300 nanometers (nm) to 1800 nm.
One or more of the following features may be included. The length may be approximately equal to a wavelength of light selected from a range of 300 nm to 1800 nm, and/or the length may be greater than 1 millimeter. The width may be approximately equal to 300 nm, to 1800 nm, or to a wavelength of light visible to a human eye selected from a range of about 300 nm to about 1800 nm. The photovoltaic device may include an active cell junction extending substantially away from the plane of the substrate.
In another aspect, embodiments of the invention include a structure for use in photonic applications. A plurality of spaced-apart photonic devices may be disposed within a device perimeter on a top surface of a substrate and may define a substrate surface area. The top surface may define a plane. Each photonic device may include an active device junction between two semiconductor materials defining an active junction surface area. The combined active surface areas of the plurality of photonic devices may be greater than the substrate surface area defined by the device perimeter.
The combined active surface areas of the plurality of photonic devices may be at least about 25% greater, 50% greater, 100% greater, 200% greater, or 400% greater than the substrate surface area defined by the device perimeter.
In another aspect, embodiments of the invention include a method of forming a structure for photonic applications. The method includes providing a non-crystalline mask over a top surface of a substrate. The mask may include a first layer disposed above and proximal to a portion of the top surface of the substrate and a second layer disposed above the first layer and above the portion of the top surface of the substrate, and the first and second layers may have a different chemical compositions. A crystalline material may be formed within an opening extending from a top surface of the mask to the top surface of the substrate to a height sufficient to permit the majority of defects arising near the interface of the crystalline material and the substrate to exit the crystalline material below the top surface of the mask layer. The second layer of the mask may be selectively removed, and a photonic device may be formed above the crystalline material.
One or more of the following features may be included. The first mask layer may include an oxide of silicon and the second mask layer may include a nitride of silicon. Forming the photonic device may include forming at least one of a multi junction photovoltaic device or a light emitting device. The photonic device may have a width of less than about one micrometer, less than about 100 nanometers, selected from a range of about 100 nanometers to about 500 nanometers, or selected from a range of about 10 nanometers to about 100 nanometers. The first mask layer may include a substantially optically reflective material or a substantially optically transparent material.
In still another aspect, embodiments of the invention include a method of forming a structure for photonic device applications. A mask layer is provided adjacent a top surface of a substrate, including at least one opening extending through the mask layer to the substrate. An intermediate crystalline material may be formed in the at least one opening, and may have a sidewall and a top surface. The material having the top surface may have a height sufficient to permit a majority of defects arising from the interface between the substrate and the first crystalline material to exit the first crystalline material below the top surface. A crystalline material may be disposed on the intermediate crystalline material to create an active photonic junction that includes sidewall regions extending in a direction away from the top surface of the substrate.
One or more of the following features may be included. Providing the first crystalline material may include providing at least one of a III-V compound, a II-VI compound, or a group IV element or compound; the III-V compound may include a III-nitride material. Providing a mask layer may include providing first and second mask layers, and may further include removing the second mask layer after forming the first crystalline material in the at least one opening. The method may further include disposing at least one third crystalline material around the crystalline material to create a second active photonic junction including a sidewall region extending in a direction away from the top surface of the substrate. The intermediate crystalline material may include a columnar sidewall or a generally planar sidewall. The generally planar sidewall may have a height generally perpendicular to the substrate and a width perpendicular to the height, and the width may be at least twice the height, at least ten times the height, or at least one hundred times the height.
The method may further include forming a photonic cell that includes the active cell junction, forming a photovoltaic cell including the active cell junction, forming a multi junction photovoltaic cell comprising the active cell junction, or forming an active cell junction below the top surface of the substrate. The photovoltaic cell may include an active cell junction disposed below the top surface of the substrate.